A floating point timer is a digital circuit that measures an interval of time by counting ticks of a reference clock signal between a start signal and a stop signal. The output of a floating point timer is a set of bits that represents the number of ticks that were counted. Mathematically, numbers can be represented in a scientific notation, mb.sup.e, where m represents a mantissa, b a base, and e an exponent. A mantissa expresses the precision (how many decimal places, for example) of a number, and an exponent expresses the range of a number (such as, to what power of ten). For example, the number 5,280 can be represented in scientific notation for base 10 as 5.280.times.10.sup.3, where 5.280 is the mantissa with four digits of precision, and 3 is the exponent, expressing a range from 1,000 up to, but not including, 10,000.
For a fixed point number, all of the bits representing the number are allocated to the mantissa, and none to the exponent. Thus, for a six-bit fixed point number, every whole number (sixty-four) in the range 0 to 63 can be represented. On the other hand, a floating point number allocates some bits to the mantissa and the remaining bits to the exponent, sacrificing precision for range. For example, a six-bit floating point number, allocating three bits to the mantissa and three bits to the exponent, can represent sixty-four whole numbers in the range 0 to 896 (7.times.2.sup.7).
Because floating point timers produce output bits for both the mantissa and the exponent, their internal circuitry is more complex, leading to difficulties in designing high resolution floating point timers using conventional circuits for generating the reference clock signal.
FIG. 1 illustrates an exemplary floating point timer using a conventional clock generation circuit, comprising a clock 100 and a divider 110. The clock 100 is typically implemented at a high-frequency crystal oscillator. Since the clock period of a high-frequency crystal oscillator is much faster than what the floating point counting circuits can handle, the crystal clock signal is divided down by divider 110 to produce a count signal as the reference clock signal.
At start time, the start signal is transmitted to reset the floating point counter logic. A mantissa counter 130 and an exponent counter 140 are set to zero, and a shift register 150 is loaded with a one (2.sup.0), which loads a pre-scaler 120 with a scaling signal indicating a one. As count signals arrive from the divider 110, they are divided by the pre-scaler 120 to produce a scaled count signal, accounting for the exponent of the floating point counter. Initially, count signals result in a corresponding scaled count signal on a one-to-one basis.
Pre-scaler 120 can be implemented as a counter for providing a plurality of divided clock signals, each at a different frequency, which are applied to a multiplexer. The scaling signal is applied to the selection input of the multiplexer to select one of the divided clock frequencies as the scaled count signal.
The scaled count signal is used to increment the mantissa counter 130, of which the most significant is a sticky bit. Once the sticky bit is set, it remains set until explicitly reset. Thus, the sticky bit ceases to count after being set. The mantissa counter 130 outputs a mantissa signal M which is indicative of the mantissa of the floating point value of the floating point timer.
When the mantissa counter 130 overflows, it outputs an overflow count signal which increments the exponent counter 140 and shifts the shift register 150 one place to the left. Incrementing the exponent counter 140 results in incrementing exponent signal E, indicative of the exponent value of the floating point timer.
Shifting the shift register 150 to the left by one place causes a new scaling value of 2.sup.E to be loaded into pre-scaler 120. Accordingly, pre-scaler 120 scales the subsequent count signal by the scaling value. For example, when the mantissa counter 130 overflows the first time after reset from the start signal, the shift register 150 contains a 2 (2.sup.0+1) and outputs a scaling signal for a scaling value of 2 to pre-scaler 120. In response, pre-scaler 120 outputs a scaled count signal for every other count signal received.
When a stop signal is generated, an output latch 160 latches the mantissa signal M from the mantissa counter 130 and the exponent signal E from the exponent counter 140. The value latched in output latch 160 is a floating point number of the form M.times.2.sup.E, representing a number of reference clock signals that have been generated in the interval of time between the start signal and the stop signal.
As mentioned earlier, the period of the reference clock signal cannot be shorter than what the floating point counting circuitry can handle, which is the worst case path through the floating point counter logic. In particular, the worst case path through the exemplary floating point counter of FIG. 1 occurs when the mantissa counter 130 overflows, causing the shift register 150 to be shifted one place to the left, outputting a new scaling signal to the pre-scaler 120. If the next count signal arrives at pre-scaler 120 before the new scaling signal in this situation, then the pre-scaler 120 is scaling the count signal by an incorrect amount.
With conventional reference clocks, the clock signal from clock 100 is divided with divider 110 by the greatest power of two so that the period of the resultant count signal is greater than the estimated worst-case delay path of the floating point counter logic. As a result, the resolution of such floating point timer can be up to half the theoretical limit, as determined by the worst-case delay path of the floating point counter logic.